System Verilog Assertions Simplified
Abstract
An assertion is a very powerful feature of System Verilog HVL (Hardware Verification Language). Nowadays it is widely adopted and used in most of the design verification projects.
This article explains the concurrent assertions syntaxes, simple examples of their usage and details of passing and failing scenarios along with waveform snippets for the ease of understanding.
This article is helpful to anyone who is new to system verification and who wishes to learn System Verification (SV) assertions quickly with simple examples. It is also useful to an experienced person who would like to have a quick refresh before he/she starts implementing it after some break.
Introduction
Irrespective of the verification methodology used in a project, System Verilog assertions help speed up the verification process. Identifying the right set of checkers in verification plan and implementing them using effective SV assertions helps to quickly catch the design bugs and ultimately helps in high-quality design.
Some of the key advantages of SV assertions are as mentioned below:
Multiple lines of checker code can be represented in a few lines effectively using SVA code.SVA can be ignored by synthesis.Assertion takes lesser time to debug as they pin point the exact time of failure. Assertions can be turned on/off during simulations. They can have severity levels; failures can be non-fatal or fatal errors.Multi-Clock assertions are useful in writing checkers around Clock Domain Crossing (CDC) logicAssertions can be also used for formal verification.
Let us look at different types of examples of SV assertions... To be continued.
An assertion is a very powerful feature of System Verilog HVL (Hardware Verification Language). Nowadays it is widely adopted and used in most of the design verification projects.
This article explains the concurrent assertions syntaxes, simple examples of their usage and details of passing and failing scenarios along with waveform snippets for the ease of understanding.
This article is helpful to anyone who is new to system verification and who wishes to learn System Verification (SV) assertions quickly with simple examples. It is also useful to an experienced person who would like to have a quick refresh before he/she starts implementing it after some break.
Introduction
Irrespective of the verification methodology used in a project, System Verilog assertions help speed up the verification process. Identifying the right set of checkers in verification plan and implementing them using effective SV assertions helps to quickly catch the design bugs and ultimately helps in high-quality design.
Some of the key advantages of SV assertions are as mentioned below:
Multiple lines of checker code can be represented in a few lines effectively using SVA code.SVA can be ignored by synthesis.Assertion takes lesser time to debug as they pin point the exact time of failure. Assertions can be turned on/off during simulations. They can have severity levels; failures can be non-fatal or fatal errors.Multi-Clock assertions are useful in writing checkers around Clock Domain Crossing (CDC) logicAssertions can be also used for formal verification.
Let us look at different types of examples of SV assertions... To be continued.
Comments
Post a Comment