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The use of mixed-signal processing is becoming vital among a wide variety of applications like telecommunication, networking, sensor chips, etc. In many designs, we have seen phase-shifted clocks being used by RTL designers. In a case where two flops are driven by phase-shifted clocks, we may not need to fix hold violations between them. When these flops are stitched together in a scan-chain using a single scan_clk, we will have hold violation during stuck-at capture. This leads to X-propagation through the compressor logic, causing coverage-loss. This article describes the challenges faced during DFT implementation for the above scenario. Phase-Shifted Clocks As a part of mixed-signal processing, many of the design uses phase-shifters circuits, which changes the phase-shift of the inputs by x degree. Below is one example of the phase-shifted clocks. DOWNLOAD CASE STUDY Design for Testability (DFT) of a Motion Control MEMS ASIC Download Now In the aspect of VLSI, consider a design wher...

Abstract An assertion is a very powerful feature of System Verilog HVL (Hardware Verification Language). Nowadays it is widely adopted and used in most of the design verification projects. This article explains the concurrent assertions syntaxes, simple examples of their usage and details of passing and failing scenarios along with waveform snippets for the ease of understanding. This article is helpful to anyone who is new to system verification and who wishes to learn System Verification (SV) assertions quickly with simple examples. It is also useful to an experienced person who would like to have a quick refresh before he/she starts implementing it after some break. Introduction Irrespective of the verification methodology used in a project, System Verilog assertions help speed up the verification process. Identifying the right set of checkers in verification plan and implementing them using effective SV assertions helps to quickly catch the design bugs and ultimately help...

The developments in the past in chip design laid the foundation for lower technology nodes that will improve power, area, and cost function. At every new node: 28nm, 16nm, 7nm, 5nm…. new challenges, tools and standards are emerging. As Lower technology node migration has expanded the reach to new deployment and business models, the  microarchitecture design fueling the next-gen ASICs , and SoCs. Today, eInfochips is working on many 7nm, 16nm ASIC tape-outs that will continue to power multiple applications in networking, artificial intelligence, machine learning, etc. Here is an infographic that defines the journey of eInfochips towards lower technology nodes: This blog is originally published at eInfochips Insights .

Watch this video to know about 7nm physical design (RTL- to - GDSII) challenges in the semiconductor industry. With proven physical design flow, methodologies and with SME experts, eInfochips working on several projects from 180nm to 7nm technology node.